`timescale 1ns / 1ps

module decoder_3_seg_sim();
	reg [3:0] binary = 4'h0;
	reg dot_ctrl = 1'b0;
	reg [31:0] i;
	wire [7:0] seg_ctrl;
	
	decoder_3_seg UUT(.binary(binary), .dot_ctrl(dot_ctrl), .seg_ctrl(seg_ctrl));
	
	initial begin
		for (i = 1 ; i<100 ; i=i+1) begin
		    if (i==20) begin dot_ctrl <= 1'b1; end
		    else if (i==52) begin dot_ctrl <= 1'b0; end
			#5 binary = binary + 1;
		end
		#10 $finish;
	end
endmodule
